1. Field of the Invention
The present invention relates to a semiconductor memory device, a memory controller and a memory access device for accessing a semiconductor memory device.
2. Description of Related Art
Recording media for recording music contents and digital data such as image data include various types such as magnetic disks, optical disks and magneto-optical disks. A semiconductor memory card, which is one of these recording media, uses a semiconductor memory such as a flush memory as a recording element, for the purpose of miniaturizing the recording media. Therefore, as described in Japanese Patent Application Laid-open No. 2001-245249, a use of a semiconductor memory card is rapidly spread in a small portable device such as a digital still camera and a cellular phone unit. At the same time, a higher transfer rate, for example, at the time of data writing is accelerated in order to respond to demands for higher definition digital data, for example, higher-resolution image even in portable device.
In a semiconductor memory card which is built in a semiconductor memory device, a NAND-type flash memory is used as a memory. A NAND-type flash memory has a characteristic that data which has been written on the destination must be erased first before writing data so as to be in a clean state, and then data is written.
A unit for erasing data is called an erasure block managed as a block consisting of a number of sectors, each of which is the smallest accessible unit. FIG. 1 is a diagram showing an exemplary relationship between erasure blocks and sectors. In FIG. 1, a flash memory consists of N number of erasure blocks from (EB)0 to EB(N−1). One erasure block is composed of 32 sectors. Each sector is provided with a physical sector number PSN. Although it is possible to access by a sector (for example, 512 bytes), erasure processing required before writing is performed by an erasure block (16 kB).
An example of processing to erase data and write in the semiconductor memory card will be explained with reference to FIGS. 2 and 3. FIG. 2 shows, as an example of write processing, a processing procedure inside the semiconductor memory card in a case of writing data having a multiple length of an erasure block. In FIG. 2, first, the semiconductor memory card receives a command and an argument transmitted from an memory access device (S201). Next, by referring to the received command, the semiconductor memory card judges whether the command is an incorrect command being unrecognizable by itself (S202). If it is an incorrect command, the semiconductor memory card notifies the memory access device of an error and ends the processing (S203). If the command is a recognizable command, the semiconductor memory card judges whether the command is a write command (S204). If the command is other than a write command, the semiconductor memory card performs another processing corresponding to each command (S205). If it is a write command, the semiconductor memory card determines the physical address of an erasure block into which data is written in the flash memory based on information about the write position and the write size stored in the argument (S206). Next, prior to the writing, the semiconductor memory card erases data exiting in the erasure block determined in S206 in the flash memory via a memory controller (S207). Next, the semiconductor memory card receives data for one sector from the memory access device (S208). Upon completion of the data reception, the semiconductor memory card writes the received data for one sector on the flash memory (S209). In this way, the semiconductor memory card repeatedly performs the data receiving and the write processing of S208 and S209 until data writing for one erasure block is completed (S210). The semiconductor memory card repeatedly performs the data writing processing for one erasure block from S206 to S210 until data writing for the writing size designated by the memory access device is completed (S211). Upon completion of data writing for the writing size designated by the memory access device, the semiconductor memory card ends the processing.
FIG. 3 shows a processing procedure inside the semiconductor memory card in a case of data writing for one sector. In a NAND-type flash memory, it is required to erase data before data writing. Since this erasure processing can be performed only by an erasure block unit, even when data for one sector is written, it is required to perform data erasure for one erasure block. The different aspects of the data write processing in FIG. 3 from the processing in FIG. 2 are, before the data erasure for one erasure block in S307, the data is copied in different location temporarily and erased, and among pieces of data included in an erasure block into which writing is performed in S310, the copied pieces of data other than data for one sector, to be received from the memory access device, are rewritten on the erasure block determined in S306.
As shown in FIGS. 2 and 3, data write processing includes three kinds of processing in large, that is, command interpretation processing, data erasure processing and data write processing. Here, assuming a flash memory in which an overhead of command interpretation takes 3 ms, write processing for one sector takes 200 μs, and erasure processing for one erasure block (16 kB) takes 2 ms. In writing for one erasure block (16 kB) of this flash memory, processing shown in FIG. 2 is performed, and command interpretation takes 3 ms, erasure processing takes 2 ms, and write processing takes 32*200 μs, that is, 11.4 ms in total. Similarly, in writing for one sector (512B), processing shown in FIG. 3 is performed, and command interpretation takes 3 ms, erasure processing takes 2 ms, and write processing takes 200 μs plus 31*200 μs, that is, 11.4 ms in total.
In other words, the cases where 16 kB data is written and where 512B data is written take almost similar time periods. Although this example shows a case in which an extreme performance difference is caused by not taking into account the data transfer periods and the like, even in an actual flash memory, it is generally known that the writing period becomes minimum when writing is performed by erasure block unit.
Further, in a semiconductor memory card, a plurality of flash memories may be used as recording elements. FIG. 4 shows an exemplary configuration of a semiconductor memory card in which two flash memories FM1 and FM2 are built-in. In each of the two flash memories shown in FIG. 4, one erasure block consists of 32 sectors. The respective sectors existing in the two flash memories are assigned with physical sector numbers of the ascending order so that the two flash memories are switched by 32 sector units. In the case of a semiconductor memory card composed of the plural number of flash memories, it is possible to realize a high-speed access by configuring the semiconductor memory card such that read and write processing is performed in parallel to the plural number of flash memories. For example, assuming that the physical sector number in the example of FIG. 4 is PSN, when data is written on the 64 sectors from PSNO to PSN63, it is possible to write data at a high speed by writing data into two erasure blocks (EB) 0_0 and 1_0 in parallel.
FIG. 5(a) shows an example of timing of writing on one erasure block in the case where a semiconductor memory card is composed of the two flash memories shown in FIG. 4, and FIG. 5(b) shows an example of timing of writing on two erasure blocks in parallel in the same case. In FIGS. 5(a) and 5(b), T1 indicates a time period for write processing of one erasure block, and T1′+T2′ indicates a time period for write processing of two erasure blocks in parallel. That is, when data is written in twice by one erasure block at each time, the write processing time is T1*2, and when data is written on two erasure blocks in parallel, the write processing time is T1′+T2′. Since the data is written on the two flash memories in parallel in the latter case, T1 and T2′ become almost similar time periods. Therefore, in the examples of FIGS. 5(a) and 5(b), write period becomes minimum when writing is performed to the semiconductor memory card by two erasure block units.
The conventional art described above contains the following problems. That is, the transfer rate of data changes significantly depending on the used state of data recording block, the write starting position, an erasure unit and the like. In other words, writing period to a semiconductor memory card depends not only on the size of an erasure block but also on the number of flash memories used in the semiconductor memory card, the management method of the flash memory, and the like. The access performance of a semiconductor memory card differs depending on the generation and the manufacturer of the semiconductor memory card. That is, the transfer rate differs significantly depending on the inner structure of the card, and also the states of sectors, which cannot be known to the memory access device.
Therefore, when, for example, moving image recording is performed by a digital still camera or the like in real time, data write processing may not be able to follow data capture processing depending on the type of a semiconductor memory card, which may cause a case that data recording cannot be performed correctly.
To cope with this, in Japanese Patent Application Laid-open No. 2001-245249, a memory access device such as a digital still camera is so configured as to be able to obtain beforehand information such as the manufacturer's name of a semiconductor memory card to be used, the capacity of the memory card, the transfer method, and the like. Moreover, the memory access device is so configured as to, before data writing, test transfer methods beforehand, and select one transfer method among one or more transfer methods applicable to the semiconductor memory card to be used, and then perform data transfer.
However, this conventional memory access device does not have a unit for acquiring the inner state of the semiconductor memory card, that is, the use state of data recording blocks, a data writing and erasing unit being unique to the semiconductor memory card, and the like. Therefore, in the transfer test of the conventional art, there is a shortcoming that accurate transfer rate information cannot be obtained.